1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device and, more particularly, to a method for fabricating a MOS transistor using a selective silicide process.
2. Description of the Related Art
Currently, a silicide process is almost essential to fabricate a transistor used for a logic device. In the silicide process, a metal having a high melting point or a transition metal is stacked over a silicon or a polysilicon layer, and heat-treated to form a silicide, an alloy of metal and silicon. By using a silicide as an electrode material, an electrode resistance is lowered, and therefore, silicides contribute greatly to enhance a switching speed of a logic device which requires a high speed.
FIGS. 1 through 4 are sectional views illustrating a method for fabricating a MOS transistor using a conventional selective silicide process.
Referring to FIG. 1, a gate insulating layer 110 and a gate polysilicon layer 120 are sequentially formed on a silicon substrate 100. After forming the gate polysilicon layer 120, impurity ions are firstly lightly implanted, using the gate polysilicon layer 120 as an ion implantation mask. Following this, a gate spacer 130 is formed on the sidewall of the gate polysilicon layer 120. Then, after impurity ions are secondly deeply implanted, using the gate polysilicon layer 120 and the gate spacer 130 as an ion implantation mask, the implanted impurity ions are diffused to form source/drain regions 140 of a lightly doped drain (LDD) structure. Then, a metal layer 150 is formed on the entire surface of the resultant structure having source/drain regions 140.
Referring to FIG. 2, a predetermined annealing process is performed on the resulting structure having the metal layer 150 to make the metal layer 150 react with silicon atoms of the gate polysilicon layer 120 and the source/drain region 140. After the annealing is completed, a first silicide layer 161 is formed on the gate polysilicon layer 120, and a second silicide layer 162 is formed on the source/drain region 140. The metal layer 150 which is not in contact with the gate polysilicon layer 120 and the source/drain region 140 does not react with the silicon atoms. Accordingly, after the first and second silicide layers 161 and 162 are formed, the portions of the metal layer which did not react are removed.
Referring to FIG. 3, an interdielectric layer 170 is formed to cover the entire surface of the resultant structure having the first and second silicide layers 161 and 162. Then, the interdielectric layer is planarized by a planarizing process like chemical mechanical polishing (CMP).
Referring to FIG. 4, contact holes are respectively formed in the interdielectric layer 170 to expose a part of the first silicide layer 161 and a part of the second silicide layer 162, and gate electrodes 181 and source/drain electrodes 182 are formed using metals. The resistance of the gate electrodes 181 and the source/drain electrodes 182 is lessened due to the existence of the first and second silicide layers 161 and 162, and, as a result, the operation speed of a device is enhanced.
However, the above method has the following problems.
First, the step of annealing the metal layer 150 over the silicon substrate 100 in order to form the first and second silicide layers 161 and 162, is performed at a high temperature, so that defects such as dislocations and crystal destruction can be generated in the region of the interface between the silicon substrate 100 and the metal layer 150. Second, a leakage current can be generated by heat treatment at a high temperature to form the first and second silicide layers 161 and 162. Third, after forming the first and second silicide layers 161 and 162, the profile of the gate polysilicon layer 120 can be changed by a chemical solution used for removing the metal layer 150 which does not react with the silicon atoms. Fourth, after forming the first and second suicide layers 161 and 162, the interdielectric layer 170 must be formed, to a thickness sufficient to protect the first silicide layer 161 in the following process.
In particular, for the MOS transistor, used in logic circuits which do not require high speed, forming the silicide layer over the source/drain region 140 does not have a great influence on the characteristics of the device operation speed. Accordingly, the silicide layer must be formed selectively in order not to affect the silicon substrate 100.
It is a feature of an embodiment of the present invention to provide a method for fabricating a MOS transistor using a selective silicide process so as not to produce defects in a silicon substrate.
In a preferred embodiment of the present invention, there is provided a method for fabricating a MOS transistor using a selective silicide process, including the following steps. A gate insulating layer and a gate polysilicon layer are sequentially formed on a substrate. Gate spacers are formed on the sidewalls of the gate insulating layer and the gate polysilicon layer. Impurity ions are implanted and diffused, using the gate spacers and the gate polysilicon layers as implant mask layers, to form a source/drain region in the silicon substrate. An etching blocking layer is formed to cover the source/drain region, the gate spacer and the gate polysilicon layer. A dielectric layer to cover the etching blocking layer is formed. The dielectric layer is planarized, and the etching blocking layer on the gate polysilicon layer is exposed. A part of the exposed etching blocking layer and a part of the gate spacer are etched, and a top surface and a top side of the gate polysilicon layer become exposed. A silicide layer is formed over the exposed part of the gate polysilicon layer.
Preferably, the etching blocking layer is formed of a material having an etching selectivity of one or more with the dielectric layer. Also, preferably, the etching blocking layer is formed to a thickness of 10-2000 angstroms.
The step of planarizing the dielectric layer can be performed using chemical mechanical polishing or etch back.
Preferably, the step of etching the exposed etching blocking layer and a part of the gate spacer is performed until the top side of the gate polysilicon layer becomes exposed by a thickness of 1500 angstroms or less.
After the step of etching the etching blocking layer and a part of the gate spacer, the step of removing a projecting part of the dielectric layer projecting toward the top portion of the gate polysilicon layer can be further included. In this case, it is preferable that the projecting part of the dielectric layer is removed by a wet etching method.
The step of forming the silicide layer, preferably, includes, a step of forming a metal layer on the exposed part of the dielectric layer, the etching blocking layer and the gate polysilicon layer, a step of heat-treating the resultant structure having the metal layer and forming a silicide layer between the gate polysilicon layer and the metal layer, and a step of removing the part of the metal layer which does not react during the heat treatment.
In the present invention, it is preferable to further include a step of forming an interdielectric layer over the resultant structure having the silicide layer, a step of patterning the interdielectric layer and forming contact holes which expose a part of the source/drain regions and a part of the suicide layer respectively, and a step of forming source/drain electrodes and gate electrodes respectively to contact the source/drain region and the silicide layer through the contact holes.
Also, it is preferable to further include a step of lightly implanting impurity ions, using the gate polysilicon layer as an ion injection mask after forming the gate polysilicon layer.